Systems in which many devices share a common resource utilize allocation arrangements for scheduling control of the resource by each device requesting such control. Resource allocation arrangements respond to requests from the devices for access to the resource. Requests are ordered according to a predetermined criterion. Control of the resource is transferred sequentially from one device to another based on the established order.
One criterion used for ordering requests is first-come, first-served. That is, a device, requesting control of the resource, assumes control of the resource before each device making a subsequent request. U.S. Pat. No. 3,638,198 issued to E. Balogh, Jr. on Jan. 25, 1972 discloses a centralized bus allocation arrangement utilizing a first-come, first-served criterion in apparatus called a bus master. The bus master inserts each request in a stack below all previously received requests. When a particular request reaches the top of the stack, control of the bus is transferred to the device which made the particular request. Since each request is associated with a particular device, identifying data about the device, including a device address, are transmitted to the bus master for storage in the stack. Consequently, for efficient, rapid operation in the bus allocation arrangement, a large number of data bus lines must be dedicated for parallel transmission of the identifying data from the requesting devices. Serial transmission is overly time consuming.
U.S. Pat. No. 4,017,841 issued to E. D. Jensen on Apr. 12, 1977 discloses an arrangement utilizing a minimal number of data dedicated bus lines for operation of the data bus allocation arrangement. Jensen discloses a bus allocation system in which devices access a data bus in a fixed, predetermined priority sequence without utilizing a bus master. Each device is assigned at least one predetermined priority. Synchronous counters in each of the devices count through each priority once during every count cycle to allow each device access to the data bus. Thus, each device is allowed access to the data bus without regard to whether a request for such access was actually made. The counters are inhibited from counting when any device accesses the data bus. In this arrangement, it is possible that a device awaiting access to the data bus will be delayed in gaining that access until the counter reaches the predetermined priority of that device. Therefore, a considerable delay is introduced between consecutive accesses by different devices.